The interest in single electron devices, and in particular single electron memories, has over the last couple of years shown a significant increase. The interest for the data storage applications is arising primarily from the seemingly ever increasing demand for faster and more densely packed memories in combination with recent reports indicating that such memories are technologically achievable. Compared to the today most used nonvolative memories for handheld devices, flash memories, memories based on single-electron devices have the potential of offering extremely dense memories since the devices are of nanoscale dimensions. Another advantage is very low power consumption due to the fact that only a very limited number of electrons are involved in the basic operations, which also can give very fast operation. The term “single electron memory” is somewhat misleading in that more than one electron may be used for representing a state (bit), although involving order of magnitudes less electrons than conventional memories. Hereinafter the term “single electron memory” should be interpreted as also comprising devices wherein a plurality, but a comparable small number, of electrons are used to represent a state. Alternatively, which also is encompassed by the term “single electron memories”, the absence of electrons, i.e. positive charge, is used for the representation. A small number in this context is below thousands of electrons/charges.
The realization of single electron devices has become possible through the advances in nanotechnology techniques and processes now providing structures that range in size from small devices of atomic dimensions, to much larger structures for example on the microscopic scale. Commonly, such structures include “nanostructures”. In certain contexts nanostructures are considered to be those having at least two dimensions not greater than about 100 nm. Nanostructures include one-dimensional nanoelements, essentially in one-dimensional form, that are of nanometer dimensions in their width or diameter, and that are commonly known as nanowhiskers, nanorods, nanowires, nanotubes, etc.
In regard to data storage, there have been proposals, and devices constructed, operating on the principle of storage of a single electron in an array of conductive islands separated by tunnel barriers, referred to as multiple tunnel junction (MJT) memories. The basic principle, to be exploited for the memory functionality, is that charge that is introduced to the structure by applying a voltage, can be confined to one part of the memory structure for an extended time, due to the tunnel barriers giving an energy barrier and thus a metastable state is formed. The presence of the charge, which can be detected by for example a field effect transistor, may represent a state (bit). A comprehensive overview is given in section 3.4 “Single Electron Trap” of Chapter II “Electronics below 10 nm”, Likharev pp. 27-68 of “Nano and Giga challenges in nanoelectronics”, Greer et al (Elsevier 2003). Implementations of such structures are disclosed in for example: Dutta et al, APL vol. 75, no. 10 6 Sep. 1999, pp. 1422-1424 “Silicon-based single electron memory using a multiple-tunnel junction fabricated by electron-beam direct writing”; Stone et al, APL vol. 73 no. 15, 12 Oct. 1998, pp. 2134-2136 “Silicon single electron memory cell”.
U.S. Pat. No. 6,126,654 and Likharev et al, APL 73, 15 12 Oct. 1998 pp. 2137-9 “Layered tunnel barriers for nonvolatile memory devices” disclose a read/write head for scanning a two-dimensional array of nanometer sized particles, small groups of such particles forming individual storage devices.
In U.S. Ser. No. 11/359,410 nanowires or nanowhiskers, are used in a data storage device. The nanowires comprise a sequence of axial segments of materials of different band gaps, arranged to provide a sequence of conductive islands separated by tunnel barriers. A storage island is formed in one end of the conductive island/tunnel barrier sequence, to provide data storage capability.
H. Nilsson et al, Applied Physics Letters 89, 163101, 2006, disclose a nanowire-based multiple quantum dot memory. Charge is injected in a nanowire comprising a multiple tunnel barrier structure formed by a quantum dots. The multiple tunnel barrier structure makes it possible to store the charge. The memory further comprises a field effect transistor read out circuit.